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| IS64C6416 FEATURES High-speed access time: 15 and 20 ns CMOS low power operation TTL compatible interface levels Single 5V 10% power supply Fully static operation: no clock or refresh required * Three state outputs * Industrial temperature available * Available in 44-pin SOJ package and 44-pin TSOP (Type II) * * * * * ISSI ADVANCED INFORMATION JANUARY 2003 (R) DESCRIPTION The ISSI IS64C6416 is a high-speed, 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS64C6416 is packaged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64K x 16 MEMORY ARRAY VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 1 IS64C6416 PIN CONFIGURATIONS 44-Pin SOJ A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC ISSI 44-Pin TSOP (Type II) A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC (R) PIN DESCRIPTIONS A0-A15 I/O0-I/O15 CE OE WE LB UB NC Vcc GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 IS64C6416 TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 (R) Vcc Current 1 2 3 4 Write ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -65 to +150 1.5 20 Unit V C W mA 5 6 7 8 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Options A1 A2 A3 Ambient Temperature -40C to +85C -40C to +105C -40C to +125C VCC 5V 10% 5V 10% 5V 10% 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 3 IS64C6416 ISSI Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.5 -0.5 GND VIN VCC GND VOUT VCC, Outputs Disabled -2 -2 Max. -- 0.4 VCC + 0.5 0.8 2 2 V V V V A A (R) DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Unit Notes: 1. VIL (min.) = -3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = MAX VCC = Max., VIN = VIH or VIL CE > VIH , f = max VCC = Max., CE > VCC - 0.2V, VIN > VCC - 0.2V, or VIN 0.2V, f = 0 A1 A2 A3 A1 A2 A3 A1 A2 A3 -15 Min. Max. -- -- -- -- -- -- -- -- -- 250 -- -- 50 -- -- 5 -- -- -20 Min. Max. -- -- -- -- -- -- -- -- -- -- 255 260 -- 55 55 -- 10 15 Unit mA ISB1 mA ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 IS64C6416 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 ISSI (R) 1 2 3 AC TEST LOADS 480 5V 480 5V 4 5 OUTPUT 30 pF Including jig and scope 255 OUTPUT 5 pF Including jig and scope 255 6 7 Figure 1 Figure 1 8 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 5 IS64C6416 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -15 Min. Max. 15 -- 3 -- -- 0 0 0 3 -- 0 0 -- 15 -- 15 7 6 -- 6 -- 7 6 -- -20 Min. Max. 20 -- 3 -- -- 0 0 0 3 -- 0 0 -- 20 -- 20 9 8 -- 8 -- 9 8 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ISSI (R) tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB tLZB Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 IS64C6416 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) ISSI (R) 1 2 t OHA t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID DATA VALID READ1.eps 3 4 READ CYCLE NO. 2(1,3) t RC ADDRESS 5 t OHA t AA OE 6 7 8 t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE LB, UB DOUT HIGH-Z t LZB t BA DATA VALID t HZB UB_CEDR2.eps 9 10 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 7 IS64C6416 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -15 Min. Max. 15 10 10 0 0 10 10 10 7 0 -- 3 -- -- -- -- -- -- -- -- -- -- 7 -- -20 Min. Max. 20 12 12 0 0 12 12 12 9 0 -- 3 -- -- -- -- -- -- -- -- -- -- 9 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ISSI (R) tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE tLZWE (2) (2) Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE =High) WE Pulse Width (OE=Low) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 IS64C6416 AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) WE ISSI (R) 1 t WC 2 t HA ADDRESS VALID ADDRESS t SA CE t SCE 3 4 5 WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE 6 t HD DATAIN VALID UB_CEWR1.eps t SD DIN 7 8 9 10 11 12 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 9 IS64C6416 WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI t HA (R) OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 IS64C6416 ISSI t WC t WC ADDRESS 2 ADDRESS 1 (R) WRITE CYCLE NO. 4 (UB/LB Back to Back Write) 1 2 ADDRESS OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA 3 4 UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD 5 UB_CEWR4.eps 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 11 IS64C6416 ORDERING INFORMATION Temperature Range (A1): -40C to +85C Speed (ns) 15 Order Part No. IS64C6416-15TA1 IS64C6416-15KA1 Package ISSI 44-pin TSOP (Type II) 44-pin 400-mil Plastic SOJ (R) Temperature Range (A2): -40C to +105C Speed (ns) 20 Order Part No. IS64C6416-20TA2 IS64C6416-20KA2 Package 44-pin TSOP (Type II) 44-pin 400-mil Plastic SOJ Temperature Range (A3): -40C to +125C Speed (ns) 20 Order Part No. IS64C6416-20TA3 IS64C6416-20KA3 Package 44-pin TSOP (Type II) 44-pin 400-mil Plastic SOJ 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00A 01/07/03 |
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